Hitherto, an antenna switch ANT-SW using a PIN diode is generally used. In recent years, an FET (Field Effect Transistor), particularly, an HEMT (High Electron Mobility Transistor) of a heterojunction structure having low on resistance is used in an antenna switch ANT-SW. By using an FET, an antenna switch ANT-SW can be integrated as a monolithic microwave integrated circuit (MMIC).
In the case of using a depletion type FET having an n channel such as an HEMT device in an antenna switch ANT-SW, a high potential difference equal to or larger than a threshold bias is applied across the gate and the source of an FET to be turned on and, on the other hand, a low potential difference equal to or less than the threshold bias is applied across the gate and the source of an FET to be turned off.
Patent document 1 (Japanese Unexamined Patent Application Publication No. H09-200021) discloses a method of improving an insertion loss characteristic and an isolation characteristic of an antenna switch ANT-SW by supplying a low bias which is lower than a ground potential as a control signal of low bias applied at the time of transmission to the gate pole of a field effect transistor of a depletion type of a reception-side switch unit of the antenna switch ANT-SW.
FIGS. 13A and 13B are diagrams showing the antenna switch ANT-SW described in the patent document 1, a control circuit, and a negative bias generation circuit.
In FIG. 13B, an antenna switch ANT-SW 4a coupled to an antenna port 5 includes a transmission-side switch (Tx switch) 4b and a reception-side switch (Rx switch) 4c. A reception-side (Rx) input port 63 of the Rx switch 4c is connected to a reception-side attenuator 6. A control circuit 10a is coupled to a control signal input port 64 of the Tx switch 4b, a control signal input port 65 of the Rx switch 4c, and the reception-side attenuator 6, and a negative bias generation circuit 9 is coupled to the control circuit 10a. Therefore, at the time of transmission, a negative bias Vss generated from the negative bias generation circuit 9 is supplied to the gate pole of a field effect transistor 71 of the depletion type of the Rx switch 4c via an output buffer 18b of the control circuit 10a. 
The negative bias generation circuit 9 shown in FIG. 13A includes an oscillator or an external input signal buffer 21, a drive circuit 22, a charge pump 23 that generates the negative bias Vss, and a level control circuit 24.
Patent document 2 (Japanese patent laid-open No. 2006-173754) discloses a method of improving the isolation characteristic and reducing power consumption in receiving operation and reception waiting operation by coupling a negative bias circuit to the gate of a depletion-type field effect transistor of a reception-side switch of an antenna switch ANT-SW. The negative bias circuit described in the patent document 2 includes an oscillator and a charge pump circuit.
Patent document 3 (WO 2008/056747) discloses a method of coupling a DC boost circuit to the gate of a field effect transistor (FET) of a Tx switch of an antenna switch ANT-SW and supplying a DC control bias and an RF signal to the DC boost circuit. With the configuration, a DC output bias larger than the DC control bias is generated from the DC boost circuit to drive the gate of the FET. By a large DC output bias, the on resistance of the FET of the Tx switch is reduced, and an RF signal loss is reduced. On the other hand, a gate to source bias of each of FETs of other switches becomes a deep reverse bias, so that a change in the gate capacitance of each FET can be reduced, and a harmonic distortion of the antenna switch ANT-SW can be reduced.
FIGS. 12A and 12B are diagrams showing the antenna switch ANT-SW and the DC boost circuit described in the patent document 3.
The DC boost circuit described in the patent document 3 is constructed as shown in FIG. 12B and operates as follows. When a coupling point 105 has a negative bias swing for the first time by an RF input signal RFin of an RF input terminal 101, a diode 108 is forwardly biased and enters a conduction state. On the other hand, a diode 109 is reversely biased and enters an unconduction state. At this time, current flows in a capacitance 106 via the diode 108, and the coupling point 105 side of the capacitance 106 is charged with negative bias. On the other hand, the side of the diodes 108 and 109 of the capacitance 106 is charged with positive bias. When the coupling point 105 has a positive bias swing, the diode 108 is reversely biased and enters an unconduction state. On the other hand, the diode 109 is forwardly biased and enters a conduction state. At this time, positive charges in the capacitance 106 flow in a capacitance 110 via the diode 109, one end of the capacitance 110 coupled to the cathode of the diode 109 is charged with positive bias. On the other hand, the other end of the capacitance 110 coupled to a DC control bias Vdc and the anode of the diode 108 is charged with negative bias. By repetition of the operation, the capacitance 110 is charged, and a boosted output bias Vout equal to the sum of the DC control bias Vdc applied to a DC control bias supply port 103 and a charge bias across both ends of the capacitance 110 is output from an output port 104 of a DC boost circuit and used for on/off control on the FET in the antenna switch ANT-SW.
Specifically, in the antenna switch ANT-SW shown in FIG. 12A, in a transmission (Tx) mode of a first RF transmission (Tx) signal Tx1, a first Tx DC control bias of the high level is supplied to a first Tx control port 310 of a first Tx switch 302. On the other hand, the first RF Tx signal Tx1 is applied to a first Tx port 306. Using a part of the first RF Tx signal Tx1, a capacitance 335 of a first DC boost circuit 330 is charged. Positive bias is applied from the capacitance 335 of the first DC boost circuit 330 to the gates of FETs 320A to 320D of the first Tx switch 302, and a gate to source bias of each of the FETs increases. Accordingly, the on resistance Ron of the FETs 320A to 320D controlled to be on in the first Tx switch 302 is reduced, and an RF signal loss in the Tx mode can be reduced. In the Tx mode of the first RF Tx signal Tx1, the second Tx DC control bias of the low level is supplied to a second Tx control port 311 of a second Tx switch 303, a first Rx DC control bias of the low level is supplied to a first Rx control port 312 of a first Rx switch 304, and a second Rx DC control bias of the low level is supplied to a second Rx control port 313 of a second Rx switch 305. Therefore, FETs 340A to 340D of the second Tx switch 303, FETs 360A to 360D of the first Rx switch 304, and FETs 370A to 370D of the second Rx switch 305 enter the off state.
In response to a DC boost output bias of the high level from the first DC boost circuit 330 of the first Tx switch 302, the bias of a common input/output port 301 of the antenna switch ANT-SW also becomes the high level. Therefore, the gate to source bias of each of the FETs 340A to 340D of the second Tx switch 303, the FETs 360A to 360D of the first Rx switch 304, and the FETs 370A to 370D of the second Rx switch 305 in the off state where the DC control bias of the low level is supplied to the gate becomes a deep reverse bias. As a result, a change in the gate capacitance of the FETs in the off state can be made small, and harmonic distortion of the antenna switch ANT-SW can be reduced.